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d a t a sh eet product speci?cation file under integrated circuits, ic12 1998 jun 18 integrated circuits om4068 lcd driver for low multiplex rates
1998 jun 18 2 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 features single-chip lcd controller/driver static/duplex/triplex drive modes with up to 32/64/96 lcd segments drive capability per device selectable backplane drive configuration: static or 2 or 3 backplane multiplexing selectable display bias configuration drive: static, 1 2 or 1 3 32 segment drivers serial data input (word length 32 to 96 bits) on-chip generation of intermediate lcd bias voltages 2 mhz fast serial bus interface cmos compatible compatible with any 4-bit, 8-bit or 16-bit microprocessors/microcontrollers may be cascaded for large lcd applications logic supply voltage range (v dd - v ss ) of 2.5 to 5.5 v display supply voltage range (v lcd - v ss ) of 3.5 to 6.5 v low power consumption, suitable for battery operated systems no external components needed by the oscillator manufactured in silicon gate cmos process. applications telecom equipment portable instruments alarm systems automotive equipment. general description the om4068 is a low-power cmos lcd driver, designed to drive liquid crystal displays (lcds) with low multiplex rates. it generates the drive signals for any static or multiplexed lcd containing up to three backplanes and up to 32 segment lines and can be easily cascaded for larger lcd applications. all necessary functions for the display are provided in a single chip, including on-chip generation of lcd bias voltages, resulting in a minimum of external components and lower power consumption. a 3-line bus structure enables serial data transfer with most microprocessors/microcontrollers. all inputs are cmos compatible. ordering information notes 1. gull wing package. 2. for details see chapter bonding pad locations. type number package name description version om4068h (1) qfp44 plastic quad ?at package; 44 leads (lead length 1.3 mm); body 10 10 1.75 mm sot307-2 om4068p dip40 plastic dual in-line package; 40 leads (600 mil) sot129-1 om4068u/5 (2) die unsawn wafer - om4068u tray chip in tray -
1998 jun 18 3 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 block diagram fig.1 block diagram. handbook, full pagewidth mbk817 backplane outputs om4068 lcd voltage selector (control logic) bp2 bp1 bp3 seg1 to seg32 (1) display segment outputs timing generator v ss v dd display latch oscillator bias voltage generator power-on reset 4 4 m0 m1 v lcd 32 4 shift register sce sclk sdin sdout (1) seg1, seg6, seg15 and seg25 are not available in dip40 package.
1998 jun 18 4 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 pinning see notes 1 to 8. symbol pin description qfp44 dip40 v lcd 4 19 lcd supply voltage v dd 5 20 positive supply voltage v ss 6 21 ground m0 7 22 drive mode select input 0 m1 8 23 drive mode select input 1 sdin 9 24 serial bus data input sclk 10 25 serial bus clock input sce 11 26 serial bus clock enable sdout 12 27 serial bus data output bp1 13 28 lcd backplane driver output 1 bp2 14 29 lcd backplane driver output 2 bp3 15 30 lcd backplane driver output 3 seg1 16 - lcd segment driver output 1 seg2 17 31 lcd segment driver output 2 seg3 18 32 lcd segment driver output 3 seg4 19 33 lcd segment driver output 4 seg5 20 34 lcd segment driver output 5 seg6 21 - lcd segment driver output 6 seg7 22 35 lcd segment driver output 7 seg8 23 36 lcd segment driver output 8 seg9 24 37 lcd segment driver output 9 seg10 25 38 lcd segment driver output 10 seg11 26 39 lcd segment driver output 11 seg12 27 40 lcd segment driver output 12 seg13 28 1 lcd segment driver output 13 seg14 29 2 lcd segment driver output 14 seg15 30 - lcd segment driver output 15 seg16 31 3 lcd segment driver output 16 seg17 32 4 lcd segment driver output 17 seg18 33 5 lcd segment driver output 18 seg19 34 6 lcd segment driver output 19 seg20 35 7 lcd segment driver output 20 seg21 36 8 lcd segment driver output 21 seg22 37 9 lcd segment driver output 22 seg23 38 10 lcd segment driver output 23 seg24 39 11 lcd segment driver output 24 seg25 40 - lcd segment driver output 25 seg26 41 12 lcd segment driver output 26
1998 jun 18 5 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 notes 1. seg1 to seg32 (lcd segment driver outputs) output the multi-level signals for the lcd segments. 2. bp0, bp1 and bp2 (lcd backplane driver outputs) output the multi-level signals for the lcd backplanes. 3. v lcd (lcd power supply): power supply for the lcd. 4. sdin (serial data line): input for the bus data line. 5. scl (serial clock line): input for the bus clock line. 6. sdout (serial data output): output of the shift register to allow serial cascading of the om4068 with other devices. 7. sce (serial clock enable): input for enable/disable acquisition on the data input line. if disabled, data on the serial bus are not accepted by the device. 8. m0 and m1 (display mode select inputs): inputs to select the lcd drive configurations; static, duplex or triplex. seg27 42 13 lcd segment driver output 27 seg28 43 14 lcd segment driver output 28 seg29 44 15 lcd segment driver output 29 seg30 1 16 lcd segment driver output 30 seg31 2 17 lcd segment driver output 31 seg32 3 18 lcd segment driver output 32 symbol pin description qfp44 dip40
1998 jun 18 6 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 fig.2 pin configuration (qfp44). handbook, full pagewidth om4068h mbk814 1 seg30 seg31 seg32 m0 m1 sdin sclk sce sdout bp1 bp2 bp3 seg1 seg2 seg3 seg4 seg5 seg6 seg7 seg8 seg9 seg10 seg11 seg12 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg21 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 v lcd v dd v ss 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
1998 jun 18 7 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 fig.3 pin configuration (dip40). handbook, halfpage om4068p mbk815 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 seg13 seg12 seg14 seg11 seg16 seg10 seg17 seg9 seg18 seg8 seg19 seg7 seg20 seg5 seg21 seg4 seg22 seg3 seg23 seg2 seg24 bp3 seg26 bp2 seg27 bp1 seg28 sdout seg29 sce seg30 sclk seg31 sdin seg32 m1 v lcd m0 v dd v ss
1998 jun 18 8 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 functional description the om4068 is a low-power lcd driver designed to interface with any microprocessor/microcontroller and a wide variety of lcds. it can drive any static or multiplexed lcd containing up to three backplanes and up to 96 segments. the display configurations possible with the om4068 depend on the number of active backplane outputs required; a selection of display configurations is given in table 1. a typical system (mux 1 : 3) is shown in fig.4. table 1 selection of display con?gurations number of 7-segments numeric dot matrix backplanes display segments digits indicator symbols 3 96 12 12 96 dots (3 32) 2 64 8 8 64 dots (2 32) 1 32 4 4 32 dots (1 32) fig.4 typical system configuration. handbook, full pagewidth host microprocessor/ microcontroller sclk sdout sce sdin 32 segment drivers (1) 3 backplanes lcd panel (up to 96 elements) om4068 m1 m0 v dd v dd v lcd v ss v ss mbk818 (1) 28 segment drivers for dip40 package. the host microprocessor/microcontroller maintains the 3-line bus communication channel with om4068. the internal oscillator requires no external components. the appropriate intermediate biasing voltage for the multiplexed lcd waveforms are generated on-chip. the only other connections required to complete the system are to the power supplies (v ss , v dd and v lcd ) and suitable capacitors to decouple the v lcd and v dd pins to v ss .
1998 jun 18 9 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 power-on reset the on-chip power-on reset block initializes the chip after power-on or power failures. the om4068 resets to a starting condition as follows: all backplane and segment outputs are set to v ss (display off) all shift registers and latches are set in 3-state sdout (allowing serial cascading) is set to logic 0 (with sce low) power-down mode. data transfers on the serial bus should be avoided for 0.5 ms following power-on to allow completion of the reset action. power-down after power-on the chip is in power-down mode as long as the serial clock is not active. during power-down all static currents are switched off (no internal oscillator, no timing and no bias level generation) and all lcd-outputs are 3-stated. the power-on reset functions remain enabled. the power-down mode is disabled at the first rising edge of the serial clock sclk. lcd bias voltage generator the intermediate bias voltages for the lcd display are generated on-chip. this removes the need for an external resistive bias chain and significantly reduces the system power consumption. the full-scale lcd voltage v op equals v lcd - v ss . the optimum value of v op depends on the lcd threshold voltage (v th ) and the number of bias levels. fractional lcd biasing voltages are obtained from an internal voltage divider of three series resistors ( 1 3 bias) connected between v lcd and v ss . the centre resistor can be switched out of the circuit to provide a 1 2 bias voltage level for the 1 : 2 multiplex configuration. the bias levels depend on the multiplex rate and are selected automatically when the display configuration is selected using m1 and m0. lcd voltage selector the lcd voltage selector (control logic) coordinates the multiplexing of the lcd in accordance with the selected drive or display configuration. the operation of the voltage selector is controlled by the input pins m0 and m1 (see table 2). table 2 drive mode selection for multiplex rates of 1 : 2 three bias levels are used including v lcd and v ss . four bias level are used for the 1 : 3 multiplex rate. the various biasing configurations together with the biasing characteristics as functions of v op =v lcd - v ss and the resulting discrimination ratios (d), are given in table 3. a practical value for v op is determinated by equating v off(rms) with a defined lcd threshold voltage (v th ), typically when the lcd exhibits approximately 10% contrast. in static mode a suitable choice is v op >3v th . m1 m0 drive mode 0 0 test mode (not user accessible) 0 1 static drive (1 : 1) 1 0 duplex drive (1 : 2) 1 1 triplex drive (1 : 3)
1998 jun 18 10 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 table 3 lcd drive modes: summary of characteristics lcd drive mode waveforms the static lcd drive mode is used when a single backplane is provided in the lcd. backplane and segment drive waveforms for this mode are shown in fig.5. lcd drive mode number of lcd bias configuration backplanes levels static 1 2 static 0 1 - 1:2 2 3 1 2 0.354 0.791 2.2236 1:3 3 4 1 3 0.333 0.638 1.915 v off rms () v op ----------------------- v on rms () v op ---------------------- - d v on rms () v off rms () ----------------------- = fig.5 static drive mode waveforms (v op =v lcd - v ss ). backplane driver output segments segn segn+1 bp1 off on handbook, full pagewidth mbk819 v lcd bp1 v ss t frame v lcd seg n (off) seg - bp1 v ss v lcd v lcd 0 v - v lcd seg n + 1 (on) v ss v lcd 0 v - v lcd
1998 jun 18 11 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 1:2m ultiplex drive mode when two backplanes are provided in the lcd, the 1 : 2 multiplex mode applies, as shown in fig.6. 1:3m ultiplex drive mode when three backplanes are provided in the lcd, the 1 : 3 multiplex mode applies, as shown in fig.7. handbook, full pagewidth mbk820 v lcd 1/2v lcd bp1 bp2 v ss t frame seg - bp1 seg - bp2 t frame t frame 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd v lcd 1/2v lcd v ss seg n seg n + 1 seg n + 2 seg n + 3 v lcd 1/2v lcd v ss v lcd 1/2v lcd v ss v lcd 1/2v lcd v ss v lcd 1/2v lcd v ss 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd 1/2v lcd v lcd 0 v - 1/2v lcd - v lcd fig.6 waveforms for 1 : 2 multiplex drive mode (v op =v lcd - v ss ). backplane driver outputs segments segn segn+1 segn+2 segn+3 bp1 off on off on bp2 off off on on
1998 jun 18 12 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 handbook, full pagewidth mbk821 seg n seg n + 1 seg n + 2 seg - bp3 seg n + 3 seg n + 4 seg n + 5 seg n + 6 seg n + 7 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v 2/3v lcd - 2/3v lcd - v lcd v lcd 0 v t frame t frame t frame t frame seg - bp2 bp2 bp3 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd seg - bp1 bp1 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd 2/3v lcd v ss v lcd 1/3v lcd fig.7 waveforms for 1 : 3 multiplex drive motive (v op =v lcd - v ss ). backplane driver outputs segments n n+1 n+2 n+3 n+4 n+5 n+6 n+7 bp1 off on off on off on off on bp2 off off on on off off on on bp3 off off off off on on on on
1998 jun 18 13 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 oscillator the internal logic and the multi-level lcd drive signals of the om4068 are generated by the built-in rc oscillator. no external components are required. in order to minimize radio frequency interference, the oscillator operates with symmetrical and slew-rate limited capacitor charge/discharge. the oscillator runs continuously once the power down state after power-on has been left. interface to microprocessor unit: serial interface a three-line bus structure enables serial unidirectional data transfer with microprocessors/microcontrollers. the three lines are a serial data input line (sdin), a serial clock line (sclk) and a data line enable (sce). all inputs are cmos compatible. these lines must always be in a defined state v ss or v dd . floating inputs could damage the chip. on the bus, one data bit is transferred during each clock pulse. the data on the sdin line remains stable during the whole clock period. data changes arrive with the falling edge of the serial clock sclk (see fig.8). fig.8 bit transfer on bus. handbook, full pagewidth mbk822 data line stable; data valid change of data allowed sdin sdout sclk shift register data present on the sdin pin is shifted into a shift register with the rising edge of the serial clock sclk in a synchronous manner. the shift register serves to transfer display information from the serial bus to the (display) latch while previous data is displayed. the shift register is organized as three 32-bit shift registers. depending on the display driving mode selected (see table 3), one, two or three registers are used and cascaded resulting in a shift register length of 32, 64 or 96 bits. figure 9 shows the shift register organization with the display data bits after a shift operation is completed. the shift sequence begins with data bit d32 and finishes with data bit d1. the correspondence between the data bit numbers and the lcd display segments is shown in table 4. data from the last stage of the register is supplied to the sdout pin to allow serial cascading of the om4068 with other peripheral devices. depending on the display driving mode selected, sdout corresponds to bit 32, 64 or 96 of the register (see fig.10). data on the sdout pin is shifted out with the falling edge of the sclk clock. sdout is therefore delayed by 1 2 sclk cycle before it is applied to the sdin pin of the next ic in the serial chain (see fig.8). the clock enable sce signal must be high in order to enable the shift operation. sdout output is latched with the last data after sce returned to high (shift operation terminated). sdout is in 3-state mode when sce is low.
1998 jun 18 14 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 display latch the 96-bit display latch holds the display data while the corresponding multiplex signals are generated. there is a one-to-one relationship between the data in the display latch and the lcd segment outputs. an lcd segment is activated when the corresponding data bit in the display latch is high. display latches are in hold mode (sce high) during the shift operation to maintain the display data constant. data are latched into the display latch with the internal frame clock. thus there is a delay of up to one half frame before new data are latched after signal sce returns to zero. timing the timing of the om4068 organizes the internal data flow of the device. this includes the transfer of display data from the shift register to the display segments outputs. the timing also generates the lcd frame frequency which is derived from the clock frequency generated in the internal clock generator: f fr(lcd) f osc 2400 ------------ - = shift register con?guration fig.9 display data bit position in shift register. handbook, full pagewidth 1 d1a d32a sdin sdout 32 96-bit shift register 64 96 32-bit register driving mode: static; (m1, m0) = 01 driving mode: duplex (1 : 2); (m1, m0) = 10 d1a d1b d32a d32b sdin 32-bit register sdout 32-bit register driving mode: triplex (1 : 3); (m1, m0) = 11 d1a d1b d32a d32b sdin 32-bit register 32-bit register d1c d32c mbk823 sdout 32-bit register
1998 jun 18 15 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 fig.10 shift register structure. handbook, full pagewidth mux sdout sdin d32a d32b d32c sclk m0 m1 mbk825
1998 jun 18 16 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 table 4 relationships between data bit numbers and the lcd segment outputs segment outputs the lcd drive section includes 32 segment outputs seg1 to seg32 which should be connected directly to the lcd. the segment output signals are generated in accordance with the multiplex backplane signals and with data in the display latch. when less than 32 segments are required the unused segment outputs should be left open-circuit. segment number driving mode static duplex triplex seg1 d1a d1a d1b d1a d1b d1c seg2 d2a d2a d2b d2a d2b d2c seg3 d3a d3a d3b d3a d3b d3c seg4 d4a d4a d4b d4a d4b d4c seg5 d5a d5a d5b d5a d5b d5c seg6 d6a d6a d6b d6a d6b d6c seg7 d7a d7a d7b d7a d7b d7c seg8 d8a d8a d8b d8a d8b d8c seg9 d9a d9a d9b d9a d9b d9c seg10 d10a d10a d10b d10a d10b d10c seg11 d11a d11a d11b d11a d11b d11c seg12 d12a d12a d12b d12a d12b d12c seg13 d13a d13a d13b d13a d13b d13c seg14 d14a d14a d14b d14a d14b d14c seg15 d15a d15a d15b d15a d15b d15c seg16 d16a d16a d16b d16a d16b d16c seg17 d17a d17a d17b d17a d17b d17c seg18 d18a d18a d18b d18a d18b d18c seg19 d19a d19a d19b d19a d19b d19c seg20 d20a d20a d20b d20a d20b d20c seg21 d21a d21a d21b d21a d21b d21c seg22 d22a d22a d22b d22a d22b d22c seg23 d23a d23a d23b d23a d23b d23c seg24 d24a d24a d24b d24a d24b d24c seg25 d25a d25a d25b d25a d25b d25c seg26 d26a d26a d26b d26a d26b d26c seg27 d27a d27a d27b d27a d27b d27c seg28 d28a d28a d28b d28a d28b d28c seg29 d29a d29a d29b d29a d29b d29c seg30 d30a d30a d30b d30a d30b d30c seg31 d31a d31a d31b d31a d31b d31c seg32 d32a d32a d32b d32a d32b d32c
1998 jun 18 17 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 backplane outputs the lcd drive section includes three backplane outputs (bp1 to bp3) which should be connected directly to the lcd. the backplane output signals are generated in accordance with the selected lcd drive mode. if less than three backplane outputs are required the unused outputs should be left open-circuit. in 1 : 2 multiplex drive mode, bp3 is set to 1 2 v lcd . in static drive mode bp3 and bp2 are set to v ss . limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. equivalent to discharging a 100 pf capacitor via a 1.5 k w series resistor (human body model). 2. equivalent to discharging a 200 pf capacitor via a 0.75 m h series inductor (machine model). handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices (see handling mos devices ). symbol parameter conditions min. max. unit v dd supply voltage - 0.5 +6.5 v v lcd lcd supply voltage - 0.5 +7.5 v v i input voltage (any input) - 0.5 v dd + 0.5 v v o output voltage (bp1, bp2, bp3, s1 to s32 and v lcd ) - 0.5 v lcd + 0.5 v i i dc input current - 10 +10 ma i o dc output current - 10 +10 ma i dd , i ss , i lcd v dd , v ss or v lcd current - 50 +50 ma p tot(pack) total power dissipation per package - 500 mw p/out power dissipation per output - 10 mw t amb operating ambient temperature - 40 +105 c t stg storage temperature - 65 +150 c t j junction temperature - 150 c v es electrostatic handling note 1 - 2000 +2000 v note 2 - 150 +150 v
1998 jun 18 18 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 dc characteristics v dd = 2.5 to 5.5 v; v ss =0v; v lcd = 3.5 to 6.5 v; t amb = - 40 to +105 c; unless otherwise speci?ed. notes 1. power-down state. after power-on the chip is in power-down state as long as the serial clock is not activated. during power-down all static currents are switched off except the power-on reset block. 2. output sdout is open-circuit; inputs at v dd or v ss ; bus inactive. 3. drive mode: static, duplex and triplex. 4. lcd outputs are open-circuit, c l = 50 pf typical, inputs at v dd or v ss ; bus inactive. 5. resets all logic when v dd 1998 jun 18 19 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 ac characteristics v dd = 2.5 to 5.5 v; v ss =0v; v lcd = 5.0 v; t amb = - 40 to +105 c; unless otherwise speci?ed. note 1. all timing values are valid within the operating supply voltage and ambient temperature range and are referenced to v il and v ih with an input voltage swing of v ss to v dd . symbol parameter min. typ. max. unit f fr(lcd) lcd frame frequency (internal clock) 50 84 175 hz f osc oscillator frequency (not available at any pin) 116 224 405 khz bus timing characteristics: serial bus interface ; note 1 f sclk sclk clock frequency 0 - 2.1 mhz t sclkl sclk clock low period 190 -- ns t sclkh sclk clock high period 190 -- ns t su(d) data set-up time 100 -- ns t h(d) data hold time 100 -- ns t r sclk, sdin rise time - 10 - ns t f sclk, sdin fall time - 10 - ns t su(en)(sdeh-sclkh) enable set-up time (sde high to sclk high) 250 -- ns t su(dis)(sclkl-sdel) disable set-up time (sclk low to sde low) 250 -- ns t phl(sdout) sdout high-to-low propagation delay 100 -- ns fig.11 serial data timing. handbook, full pagewidth mbk824 t sclkh t sclkl t h(d) t su(en)(sdeh-sclkh) t su(dis)(sclkl-sdel) t su(d) t r t f t phl(sdout) sdout sclk sdin sce
1998 jun 18 20 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 bonding pad locations fig.12 bonding pad locations. dimensions in mm. bonding pad dimensions: 80 80 m m. handbook, full pagewidth mbk816 2.03 mm 2.01 mm x y 0 0 2 seg31 4 v lcd 5 v dd 6 v ss 7 m0 8 m1 9 sdin 10 11 sce 12 sdout 13 bp1 14 bp2 15 bp3 16 seg1 17 seg2 18 seg3 19 seg4 20 seg5 21 seg6 22 seg7 23 seg8 24 seg9 25 seg10 26 seg11 27 seg12 28 seg13 29 seg14 30 seg15 31 seg16 32 seg17 33 seg18 34 seg19 35 seg20 36 seg21 37 seg22 38 seg23 39 seg24 40 seg25 41 seg26 42 seg27 43 seg28 44 seg29 1 seg30 sclk 3 seg32 om4068
1998 jun 18 21 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 table 5 bonding pad locations (dimensions in m m). all x/y coordinates are referenced to bottom left corner of chip (see fig.12). symbol pad x y v dd 5 43.100 970.500 v ss 6 42.900 791.850 m0 7 43.100 661.750 m1 8 43.100 531.750 sdin 9 43.100 401.750 sclk 10 43.100 271.750 sce 11 310.450 43.100 sdout 12 447.350 43.100 bp1 13 604.800 43.100 bp2 14 714.850 43.100 bp3 15 824.850 43.100 seg1 16 924.850 43.100 seg2 17 1024.850 43.100 seg3 18 1124.850 43.100 seg4 19 1224.850 43.100 seg5 20 1327.250 43.100 seg6 21 1432.450 43.100 seg7 22 1532.650 43.100 seg8 23 1783.600 293.850 seg9 24 1783.600 458.850 seg10 25 1783.600 603.850 seg11 26 1783.600 703.850 seg12 27 1783.600 803.850 seg13 28 1783.600 903.850 seg14 29 1783.600 1003.850 seg15 30 1783.600 1103.850 seg16 31 1783.600 1203.850 seg17 32 1783.600 1323.850 seg18 33 1783.600 1453.850 seg19 34 1514.600 1711.100 seg20 35 1370.550 1711.100 seg21 36 1270.500 1711.100 seg22 37 1170.500 1711.100 seg23 38 1070.500 1711.100 seg24 39 970.550 1711.100 seg25 40 870.550 1711.100 seg26 41 770.550 1711.100 seg27 42 660.550 1711.100 seg28 43 550.550 1711.100 seg29 44 430.550 1711.100 seg30 1 300.550 1711.100 seg31 2 43.100 1460.050 seg32 3 43.100 1274.950 v lcd 4 43.100 1158.700 alignment marks c1 - 1769.6 1696.9 c2 - 1770.1 58.4 f - 172.0 1705.2 symbol pad x y
1998 jun 18 22 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 package outlines unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.25 0.05 1.85 1.65 0.25 0.40 0.20 0.25 0.14 10.1 9.9 0.8 1.3 12.9 12.3 1.2 0.8 10 0 o o 0.15 0.1 0.15 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.95 0.55 sot307-2 95-02-04 97-08-01 d (1) (1) (1) 10.1 9.9 h d 12.9 12.3 e z 1.2 0.8 d e e b 11 c e h d z d a z e e v m a x 1 44 34 33 23 22 12 y q a 1 a l p detail x l (a ) 3 a 2 pin 1 index d h v m b b p b p w m w m 0 2.5 5 mm scale qfp44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm sot307-2 a max. 2.10
1998 jun 18 23 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 unit a max. 1 2 b 1 cd e e m h l references outline version european projection issue date iec jedec eiaj mm inches dimensions (inch dimensions are derived from the original mm dimensions) sot129-1 92-11-17 95-01-14 a min. a max. b z max. w m e e 1 1.70 1.14 0.53 0.38 0.36 0.23 52.50 51.50 14.1 13.7 3.60 3.05 0.254 2.54 15.24 15.80 15.24 17.42 15.90 2.25 4.7 0.51 4.0 0.067 0.045 0.021 0.015 0.014 0.009 2.067 2.028 0.56 0.54 0.14 0.12 0.01 0.10 0.60 0.62 0.60 0.69 0.63 0.089 0.19 0.020 0.16 051g08 mo-015aj m h c (e ) 1 m e a l seating plane a 1 w m b 1 e d a 2 z 40 1 21 20 b e pin 1 index 0 5 10 mm scale note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. (1) (1) (1) dip40: plastic dual in-line package; 40 leads (600 mil) sot129-1
1998 jun 18 24 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (order code 9398 652 90011). dip s oldering by dipping or by wave the maximum permissible temperature of the solder is 260 c; solder at this temperature must not be in contact with the joint for more than 5 seconds. the total contact time of successive solder waves must not exceed 5 seconds. the device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (t stg max ). if the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. r epairing soldered joints apply a low voltage soldering iron (less than 24 v) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. if the temperature of the soldering iron bit is less than 300 c it may remain in contact for up to 10 seconds. if the bit temperature is between 300 and 400 c, contact may be up to 5 seconds. qfp r eflow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. w ave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, for qfp packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. caution wave soldering is not applicable for all qfp packages with a pitch (e) equal or less than 0.5 mm.
1998 jun 18 25 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. r epairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c. definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
1998 jun 18 26 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 notes
1998 jun 18 27 philips semiconductors product speci?cation lcd driver for low multiplex rates om4068 notes
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1998 sca60 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reli able and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors 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novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 printed in the netherlands 415106/1200/01/pp28 date of release: 1998 jun 18 document order number: 9397 750 03802

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